The present invention relates in general to power distribution on an electronic device such as, for example, an integrated circuit or printed circuit board.
In designing the layout for a semiconductor integrated circuit, there is often a need to place identical circuit blocks next to each other. This is typically done by preparing the layout for a master circuit block (e.g., containing several thousands of transistor devices), placing the master circuit block layout within the overall chip layout for the integrated circuit, and then creating and placing identical (i.e., mirror or symmetrical) images of the master circuit block on the integrated circuit layout next to the master circuit block. Several such image circuit blocks may be formed depending on the particular integrated circuit design. One of the reasons that such image circuit blocks are formed is so that input/output pins to each circuit block can be placed on the layout so that they are opposite one another to reduce the layout area required and the layout routing distance necessary to connect the input/output pins to the rest of the integrated circuit.
In placing the master and image circuit blocks, care is generally taken to ensure that input/output signals and power supply connections common to the master and image circuit blocks are implemented in a way within the overall layout design so that routing congestion is minimized and signal timing and power supply parasitics are balanced and within acceptable variations for the master and image circuit blocks.
Prior layout approaches include the use of VDD and VSS power rings within each of the master and image circuit blocks. However, the use of such power rings consumes a large amount of layout area in part due to redundancy in the resulting power supply distribution grid across the integrated circuit. Prior overall chip layout design approaches further have not integrated the use of such power rings into a comprehensive and layout-efficient, top-down power distribution layout methodology. Instead, prior approaches typically defer full-chip power integration to the end of the layout process, which results in inefficient usage of layout area for power distribution needs.
In light of the foregoing, there is a need for an improved power distribution system for an integrated circuit layout that more efficiently uses the layout area required for providing power to master and image circuit blocks and other circuits in the integrated circuit. There is a further need for such a power distribution system that readily integrates with a top-down layout design and integration process for completing the overall circuit layout and power distribution design of the integrated circuit.